IBM Demos Sub-10nm Transistor, Graphene Chip and Racetrack Memory

From X-bit Labs: Scientists from IBM on Monday unveiled several exploratory research breakthroughs that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips. The researchers demonstrated a graphene-based chip, the first transistor with sub-10 nm channel lengths as well as Racetrack memory.

For more than 50 years, computer processors have increased in power and shrunk in size at a tremendous rate. However, today’s chip designers are hitting physical limitations with Moore’s Law, halting the pace of product innovation from scaling alone. With virtually all electronic equipment today built on complementary-symmetry metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scalability limits of the silicon transistor.

Following years of key physics advances previously only achieved in a laboratory, IBM scientists successfully integrated the development and application of new materials and logic architectures on 200mm diameter wafers. These breakthroughs could potentially provide a new technological basis for the convergence of computing, communication, and consumer electronics.

“Throughout its history, IBM’s continued investment in scientific research to identify new materials and processes has not only extended current technologies but is providing a sustainable technology foundation for tomorrow. Today's breakthroughs challenge the status quo by exploring the boundaries of science and transforming that knowledge into information technology systems that could advance the power and capability of businesses worldwide,” said T.C. Chen, vice president of science and technology at IBM Research.

Racetrack memory combines the benefits of magnetic hard drives and solid-state memory to overcome challenges of growing memory demands and shrinking devices. Proving this type of memory is feasible, IBM researchers are detailing the first Racetrack memory device integrated with CMOS technology on 200mm wafers, culminating seven years of physics research.

The researchers demonstrated both read and write functionality on an array of 256 in-plane, magnetized horizontal racetracks. This development lays the foundation for further improving Racetrack memory’s density and reliability using perpendicular magnetized racetracks and three-dimensional architectures. This breakthrough could lead to a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second.

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